Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (“PIPs”). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (“PLDs”), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
As is known, a circuit design is conventionally described using a computer aided design (“CAD”), such as an Electronic Design Automation (“EDA”) tool set. Such a tool set conventionally produces what is referred to as a synthesized design, namely translated from a register transfer language (“RTL”) description, such as in a Hardware Description Language (“HDL”) such as Verilog or VHDL, among other formats, into a discrete network listing (“netlist”) of logic-gate primitives. Such a synthesized circuit design is subsequently mapped to circuit resources of a PLD, such as an FPGA. This is to ensure that there are a sufficient number of resources, such as programmable circuit resources of an FPGA, for instantiation of the circuit design. This is sometimes referred to as a “floating netlist” as actual resources of an FPGA are not allocated; rather an x-axis versus y-axis spreading of logic-gate primitives of the netlist is output from a global placement. However, even though a global placement is not actual placement of circuit resources on an FPGA grid, such global placement does produce a real-valued placement of objects, namely objects associated with logic-gate primitives, in x- and y-axes.
A placer tool for global placement uses a force directed analytical placement engine to spread a circuit design, namely primitives of a netlist. Output from a global placement phase conventionally results in design blocks with real-valued placement information sparsely overlapped. Such a global placement is used to obtain real-valued placement information for a more detailed placement.
The placer tool used for global placement may include a detailed placement engine for a fitting stage. Such detailed placement engine obtains the placement information from the global placement as input and produces a non-overlapping placement for an FPGA grid. By overlapping, it should be understood that a global placement does not take into account control set conflicts. Thus, during a global placement stage, two circuit blocks may be placed in the same site or region of an FPGA grid without taking into account that such circuit blocks are incompatibly placed due to control set conflicts.
A control set is a combination of clock and control signals associated with a block of circuitry. The control signal(s) of a control set may include one or more of an enable signal, a set signal, a reset signal, or a rev signal for FPGAs available from Xilinx, Inc., of San Jose, Calif. Control sets control sequential elements of a design, such as registers. Accordingly, each sequential element has associated therewith a control set. A hardware restriction for FPGAs, such as FPGAs from Xilinx, Inc., is that each register or lookup table random access memory (“LUTRAM”) in a “slice” of an FPGA CLB should have the same control set. If the control sets are not the same, resynthesis in some instances may be used to promote one or more related control sets, for making them compatible.
However, some control sets are not compatible with other control sets. Accordingly, only elements with the same control sets, including resynthesized compatible control sets, may be placed in a same slice. Heretofore, if during a global placement, incompatible control sets for registers were placed in a same slice, then conventionally, one of the control sets was moved and placed in an empty slice to resolve the compatibility conflict. However, this utilization of slices may have a negative impact on utilization of circuit resources.
For FPGA implementers of circuit designs, slice utilization is a considered parameter. Designers conventionally want some room in their device to add more logic, if necessary, for engineering change orders, updates, or for other types of changes. Additionally, lower slice utilization may be desirable from a standpoint of reducing routing issues. Lower slice utilization may further be beneficial from a power standpoint, as less routing resources are used outside of CLBs.
Accordingly it would be desirable and useful to provide means for a fitting that enhances slice utilization over the above-described conventional detailed placement.